1. Field of the Invention
The present invention relates, generally, to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with an improved overlay margin between stacked layers, and methods of manufacturing the same.
2. Description of the Related Art
Conventional manufacturing methods of forming dynamic random access memories (DRAMs) can be categorized as a stack-type method and a trench-type method. In the former method, an active region is formed on a silicon substrate, a gate is formed thereon using polysilicon, and then a bit line contact plug, a bit line, a storage node contact plug, and a storage node (i.e., a lower electrode of a capacitor) are formed. In the latter method, a trench is formed in a silicon substrate, and a storage node is formed therein, thereby forming a capacitor below the substrate.
For example, a conventional stack-type method is used to embody the layout of a DRAM cell region as shown in FIG. 1. FIG. 2 is a cross-sectional view of a DRAM, taken along line II-II′ of FIG. 1. Referring to FIGS. 1 and 2, active regions 2 are repeatedly arranged in rows and columns on a substrate 1. Portions of the substrate 1 other than the active regions 2 correspond to an isolation layer 3. Each pair of gates 4 are arranged to intersect one active region 2. A gap between the gates 4 is filled with a first interlayer dielectric (ILD) 5, and cell pads 6a and 6b are disposed on both sides of each gate 4 in a self-aligned contact manner. A second ILD 7 is disposed on the cell pads 6a and 6b and the gates 4, a bit line contact plug 8 is connected to the cell pad 6b adjacent to a drain, and a bit line 9 is disposed on the bit line contact plug 8 perpendicular to a direction in which the gates 4 extend. A storage node contact plug 10 is disposed on the cell pad 6a adjacent to a source, and a storage node 11 is disposed on the storage node contact plug 10.
In the foregoing stack-type method, after the narrow gap between the gates 4 is filled with the ILD 5, the storage node contact plug 10 is formed between the gates 4 and the bit lines 9 that intersect at a right angle to each other. Thus, it is difficult to increase a gap filling margin and overlay margin. Also, as the height of the storage node 11 increases to increase capacitance, the height of the stack structure also increases. Accordingly, after a capacitor forming process is finished, a step difference between a cell region and a core region increases. As a result, photolithography for a subsequent interconnection process becomes very complicated. On the other hand, in the trench-type method, as pattern pitch is reduced, a region where the storage node is formed is continuously scaled down. Thus, a trench should be formed in a silicon substrate to a larger depth, but this is reaching the technical limit.
In addition, in both of the methods, as the integration density of semiconductor devices increases and the pattern pitch decreases, it is very difficult to increase an overlay margin between stacked layers. This is because reducing the pattern pitch is reaching the resolution limit of exposure equipment.
In manufacturing of highly integrated semiconductor devices, the performance of exposure equipment cannot keep up with manufacturing technologies. Since a reduced pattern pitch reaches the resolution limit of exposure equipment, when complicated patterns are formed, yield is reduced due to poor uniformity and pattern fidelity. Therefore, a new method of precisely forming complicated patterns and increasing an overlay margin in spite of device downscaling is required.